WISHBONE I/F
s1_coreはテストベンチのトップレベルで、WISHBONEのBusを経由してROMに接続されています。
WISHBONEはOpenCores.orgで推奨されているfreeに使用できるバスの規格です。
http://www.opencores.org/projects.cgi/web/wishbone/wishbone
s1_coreではSPARCのバスサイクルを、spc2wbmでWISHBONEに変換しています。s1_coreをFPGAで動かす場合、最終的には外付けのROMをWISHBONEのI/Fで接続するか、FPGA内部のSRAMにROMを実装する必要があります。Stratix3をターゲットとするなら、後者の方が楽でしょう。
ROMの読み出し
WISHBONEのBusから見た最初の読み出し波形です。weをLにした状態で、strobeがHになるのが、リードサイクルです。ROMからは、ackをHにしてデータの読み出しを通知しています。
最初のアクセスですが、アドレスは0x800000FFF000020となっており、下位の方はリセット時のPCと同じ値です。
上位bitの意味はs1_coreのSUPPORT.txtに書かれています。
Each bit of the Address Bus has a different meaning:
- bits [63:59] specify the one-hot encoding for the T1 target region number;
- bits [58:40] are 19 bits always hardwired to zero;
- bits [39:0] are the 40-bit Physical Address as it comes from the SPARC Core.
読み出している値は、0xC0F00B0103000000です。rom_harness.hexの20番地をちゃんと読み出しています。
82102010e2f04840 a2102003e2f008a0 a3480000819c6820 82102018c0f00a01 c0f00b0103000000 8210600083287020 23000000a2144001
64bit環境なので0x20番地は5行目になります。
先頭の4行が何のデータかは気になりますが、とりあえず予想していたアドレスは読めています。
ROMの内容
同じく配布されているACCESSES.txtにBOOT CODEの逆アセがあるのですが、rom_harness.hexと内容が違います。どちらが正しいのかは分かりませんが、ACCESSES.txtはちゃんと20から始まっているので、こちらの方が正しい気がします。
参考までにACCESSES.txtの中身を張り付けておきます。
Fetches from SSI OpenBoot PROM (section RED_SEC) ================================================ fff0000020: 03 00 00 00 sethi %hi(0), %g1 fff0000024: 05 00 01 00 sethi %hi(0x40000), %g2 fff0000028: 82 10 60 00 mov %g1, %g1 fff000002c: 84 10 a0 c0 or %g2, 0xc0, %g2 fff0000030: 83 28 70 20 sllx %g1, 0x20, %g1 fff0000034: 84 10 80 01 or %g2, %g1, %g2 fff0000038: 81 c0 80 00 jmp %g2 fff000003c: 01 00 00 00 nop Fetches from RAM Bank 3 (section RED_EXT_SEC) ============================================= 00000400c0: b5 80 20 05 wr %g0, 5, %asr26 00000400c4: a2 10 20 00 clr %l1 00000400c8: 82 10 20 a9 mov 0xa9, %g1 00000400cc: 83 28 70 20 sllx %g1, 0x20, %g1 00000400d0: e2 70 60 00 stx %l1, [ %g1 ] 00000400d4: e2 70 60 40 stx %l1, [ %g1 + 0x40 ] 00000400d8: e2 70 60 80 stx %l1, [ %g1 + 0x80 ] 00000400dc: e2 70 60 c0 stx %l1, [ %g1 + 0xc0 ] 00000400e0: a2 10 20 00 clr %l1 00000400e4: 82 10 20 10 mov 0x10, %g1 00000400e8: e2 f0 48 40 stxa %l1, [ %g1 ] (66) 00000400ec: a2 10 20 03 mov 3, %l1 00000400f0: e2 f0 08 a0 stxa %l1, [ %g0 ] (69) 00000400f4: a3 48 00 00 rdhpr %hpstate, %l1 00000400f8: 81 9c 68 20 wrhpr %l1, 0x820, %hpstate 00000400fc: 87 80 20 25 wr %g0, 0x25, %asi Fetches from RAM Bank 0 (section RED_EXT_SEC) ============================================= *** BEGIN *** These 8 stores to Interrupt Queue ASI Registers were removed to obtain clean waveforms. Further investigation will follow when full support for interrupts will be added. 0000040100: c0 f0 23 c0 stxa %g0, [ 0x3c0 ] %asi 0000040104: c0 f0 23 c8 stxa %g0, [ 0x3c8 ] %asi 0000040108: c0 f0 23 d0 stxa %g0, [ 0x3d0 ] %asi 000004010c: c0 f0 23 d8 stxa %g0, [ 0x3d8 ] %asi 0000040110: c0 f0 23 e0 stxa %g0, [ 0x3e0 ] %asi 0000040114: c0 f0 23 e8 stxa %g0, [ 0x3e8 ] %asi 0000040118: c0 f0 23 f0 stxa %g0, [ 0x3f0 ] %asi 000004011c: c0 f0 23 f8 stxa %g0, [ 0x3f8 ] %asi *** END *** 0000040120: 8f 90 20 00 wrpr 0, %tl 0000040124: a1 90 20 00 wrpr 0, %gl 0000040128: 8d 80 20 00 wr %g0, 0, %fprs 000004012c: 85 80 20 00 wr %g0, 0, %ccr 0000040130: 87 80 20 00 wr %g0, 0, %asi 0000040134: 84 10 20 00 clr %g2 0000040138: 89 90 80 00 wrpr %g2, %tick 000004013c: 84 10 20 00 clr %g2 0000040140: b1 80 80 00 mov %g2, %asr24 0000040144: 84 10 20 01 mov 1, %g2 0000040148: 85 28 b0 3f sllx %g2, 0x3f, %g2 000004014c: af 80 80 00 mov %g2, %asr23 0000040150: b3 80 80 00 mov %g2, %asr25 0000040154: bf 98 80 00 wrhpr %g2, %hstick_cmpr 0000040158: 81 80 00 00 mov %g0, %y 000004015c: 91 90 20 0f wrpr 0xf, %pil 0000040160: 93 90 20 00 wrpr 0, %cwp 0000040164: 95 90 20 06 wrpr 6, %cansave 0000040168: 97 90 20 00 wrpr 0, %canrestore 000004016c: 9b 90 20 00 wrpr 0, %otherwin 0000040170: 99 90 20 07 wrpr 7, %cleanwin 0000040174: 9d 90 20 07 wrpr 7, %wstate 0000040178: 82 10 20 18 mov 0x18, %g1 000004017c: c0 f0 0a 01 stxa %g0, [ %g0 + %g1 ] (80) 0000040180: c0 f0 0b 01 stxa %g0, [ %g0 + %g1 ] (88) 0000040184: a2 10 20 03 mov 3, %l1 0000040188: e2 f0 09 60 stxa %l1, [ %g0 ] (75) 000004018c: a2 10 20 03 mov 3, %l1 0000040190: 82 10 20 aa mov 0xaa, %g1 0000040194: 83 28 70 20 sllx %g1, 0x20, %g1 0000040198: e2 70 60 00 stx %l1, [ %g1 ] 000004019c: e2 70 60 40 stx %l1, [ %g1 + 0x40 ] 00000401a0: e2 70 60 80 stx %l1, [ %g1 + 0x80 ] 00000401a4: e2 70 60 c0 stx %l1, [ %g1 + 0xc0 ] 00000401a8: a3 46 80 00 rd %asr26, %l1 00000401ac: 03 00 00 07 sethi %hi(0x1c00), %g1 00000401b0: 82 10 63 00 or %g1, 0x300, %g1 ! 1f00 <main+0x1f00> 00000401b4: a2 0c 40 01 and %l1, %g1, %l1 00000401b8: a3 34 70 08 srlx %l1, 8, %l1 00000401bc: 03 00 00 00 sethi %hi(0), %g1 00000401c0: 05 00 01 30 sethi %hi(0x4c000), %g2 00000401c4: 82 10 60 00 mov %g1, %g1 00000401c8: 84 10 a0 00 mov %g2, %g2 00000401cc: 83 28 70 20 sllx %g1, 0x20, %g1 00000401d0: 84 10 80 01 or %g2, %g1, %g2 00000401d4: a3 2c 70 03 sllx %l1, 3, %l1 00000401d8: c4 58 80 11 ldx [ %g2 + %l1 ], %g2 00000401dc: 82 10 20 80 mov 0x80, %g1 00000401e0: c4 f0 4b 00 stxa %g2, [ %g1 ] (88) 00000401e4: 2f 00 02 00 sethi %hi(0x80000), %l7 00000401e8: 8b 9d c0 00 wrhpr %l7, %htba 00000401ec: 21 00 00 00 sethi %hi(0), %l0 00000401f0: 03 00 01 30 sethi %hi(0x4c000), %g1 00000401f4: a0 14 20 00 mov %l0, %l0 00000401f8: 82 10 61 40 or %g1, 0x140, %g1 00000401fc: a1 2c 30 20 sllx %l0, 0x20, %l0 0000040200: 82 10 40 10 or %g1, %l0, %g1 0000040204: 85 28 b0 07 sllx %g2, 7, %g2 0000040208: 82 00 40 02 add %g1, %g2, %g1 000004020c: e2 58 40 00 ldx [ %g1 ], %l1 0000040210: e2 f0 06 e0 stxa %l1, [ %g0 ] (55) 0000040214: e2 58 60 08 ldx [ %g1 + 8 ], %l1 0000040218: e2 f0 07 e0 stxa %l1, [ %g0 ] (63) 000004021c: e2 58 60 10 ldx [ %g1 + 0x10 ], %l1 0000040220: e2 f0 06 a0 stxa %l1, [ %g0 ] (53) 0000040224: e2 58 60 20 ldx [ %g1 + 0x20 ], %l1 0000040228: e2 f0 06 c0 stxa %l1, [ %g0 ] (54) 000004022c: e2 58 60 18 ldx [ %g1 + 0x18 ], %l1 0000040230: e2 f0 07 a0 stxa %l1, [ %g0 ] (61) 0000040234: e2 58 60 28 ldx [ %g1 + 0x28 ], %l1 0000040238: e2 f0 07 c0 stxa %l1, [ %g0 ] (62) 000004023c: e2 58 60 40 ldx [ %g1 + 0x40 ], %l1 0000040240: e2 f0 06 60 stxa %l1, [ %g0 ] (51) 0000040244: e2 58 60 48 ldx [ %g1 + 0x48 ], %l1 0000040248: e2 f0 07 60 stxa %l1, [ %g0 ] (59) 000004024c: e2 58 60 50 ldx [ %g1 + 0x50 ], %l1 0000040250: e2 f0 06 20 stxa %l1, [ %g0 ] (49) 0000040254: e2 58 60 60 ldx [ %g1 + 0x60 ], %l1 0000040258: e2 f0 06 40 stxa %l1, [ %g0 ] (50) 000004025c: e2 58 60 58 ldx [ %g1 + 0x58 ], %l1 0000040260: e2 f0 07 20 stxa %l1, [ %g0 ] (57) 0000040264: e2 58 60 68 ldx [ %g1 + 0x68 ], %l1 0000040268: e2 f0 07 40 stxa %l1, [ %g0 ] (58) 000004026c: 94 10 20 80 mov 0x80, %o2 0000040270: c0 f2 8a e0 stxa %g0, [ %o2 ] (87) 0000040274: c0 f2 8b e0 stxa %g0, [ %o2 ] (95) 0000040278: a2 10 20 08 mov 8, %l1 000004027c: c0 f4 44 20 stxa %g0, [ %l1 ] (33) 0000040280: a2 10 20 10 mov 0x10, %l1 0000040284: c0 f4 44 20 stxa %g0, [ %l1 ] (33) 0000040288: a2 10 20 0f mov 0xf, %l1 000004028c: e2 f0 08 a0 stxa %l1, [ %g0 ] (69) 0000040290: 03 00 00 00 sethi %hi(0), %g1 0000040294: 05 00 05 10 sethi %hi(0x144000), %g2 0000040298: 82 10 60 00 mov %g1, %g1 000004029c: 84 10 a0 00 mov %g2, %g2 00000402a0: 83 28 70 20 sllx %g1, 0x20, %g1 00000402a4: 84 10 80 01 or %g2, %g1, %g2 00000402a8: 87 48 00 00 rdhpr %hpstate, %g3 00000402ac: 8f 90 20 01 wrpr 1, %tl 00000402b0: 88 10 20 00 clr %g4 00000402b4: 83 99 00 00 wrhpr %g4, %htstate 00000402b8: 8f 90 20 00 wrpr 0, %tl 00000402bc: 90 10 20 00 clr %o0 00000402c0: 81 c0 80 00 jmp %g2 00000402c4: 81 98 28 00 wrhpr 0x800, %hpstate 00000402c8: 01 00 00 00 nop 00000402cc: 01 00 00 00 nop 00000402d0: 82 10 20 0f mov 0xf, %g1 ! f <main+0xf> 00000402d4: c2 f0 08 a0 stxa %g1, [ %g0 ] (69) 00000402d8: c0 f0 08 60 stxa %g0, [ %g0 ] (67) 00000402dc: 83 48 00 00 rdhpr %hpstate, %g1
